65nm LPe

GLOBALFOUNDRIES is delivering an enhanced version of its 65-nanometer low-power process, called 65nm LPe. The new 65nm LPe process utilizes innovative leakage reduction techniques to significantly improve SoC power utilization by up to 50 percent while extending battery efficiency by up to 25 percent. The result is a lower power process especially well suited for battery-operated and cost-sensitive mobile applications. The process is also supported by a robust range of IP support specifically optimized for the lower leakage capabilities.

GLOBALFOUNDRIES also announced an optimized RF platform solution based on the 65nm LPe process, that combines RF physical design kits jointly developed with IBM, broad IP support and a collaborative development system with its partners from the Wireless SOC Platform Alliance (WISPA) consortium.

The 65nm LPe process achieves leakage reduction through a shift in the performance-to-leakage ratio (Ion/Ioff) within the process' PMOS transistors. Given the same Ion (uA/um), the Ioff current is reduced by a magnitude of 20X. This directly impacts battery life, improving the efficiency of typical operation by 15-25 percent depending on the application.

A full suite of IP is available for the new process, including analog front end (AFE), audio codecs, and standard interfaces. The system level IP, libraries and memory compilers that support the 65nm LPe process have been expanded and specifically tuned to take advantage of the enhanced leakage capabilities of the process. In addition, the comprehensive range of design enablement support available on the original GLOBALFOUNDRIES 65nm LP process from third-party EDA, IP and design services suppliers is available with the 65nm LPe process.